True Moore's Law plays a big role but techniques such as AI upscaling and this patent should help over come Moore's Law.
At least for next-gen.
Which actually reminds me of this AMD's patent.
I saw this great info you posted the other day and was getting Cell BE - particularly ring bus EiB (Elemental Interconnecting Bus) vibes from the Cerny patent of the multi-GPUs and wanted to comment.
I thought the snippet of wording in the patent seemed very interesting in regards of the vague "screen region" description.
Rather than use something more specific such as "viewport region" - if you spilt the display into just 4 viewport sections like a 4 screen video wall - or a "cascade region" - if you split the frustum like they do in cascaded shadow mapping as increasing slices, say if you split the stub nose view cone (frustum) up like a loaf of bread.
This got me thinking that the reason for the "screen region" description might be related to the main reason for needing more processing: ray tracing where the activity density is vague and fits with where ever would be appropriate for placing light probes in a game scene, essentially denoising floating point calculations in the RT rendering problem somewhat by placing a GPU at a probe location meaning the calculations are most accurate at the sources of lighting interaction and the ability to absorb or eliminate redundant work at a probe that doesn't impact, or bottleneck the other GPUs and add any latency overall to a frame, probably allowing more aggressive elimination testing per probe and then presumably trace further towards the scene light sources, improving visual quality and resulting in finer grain use of BVHs at each GPU, as a subset of the scene total BVH, further reducing data transfers,
The reason I was getting EiB/Cell BE vibes about the GPU interconnections is because I believe it is the only way you could reliably make a solution and it scale, either as a stacked set of chips with ringbuses, or as a lidded multi-chip mounted on a board solution like the WiiU chip but with the chips connected by ringbuses.
Obviously, the problem with ringbuses is that they trade higher bandwidth, peak throughput and lower latency of the less complex crossbar bus for scalability and deterministic throughput. So that would still lean towards a crossbar bus, but given the locality of the memory modules to each GPU and appearing owned by a GPU as a split memory, a ringbus could easily abstract that separation to make them appear unified, and by using multiple rings, probably 4 - with at least 1 starting at each GPU and being a GPU-to-GPU timeslice starting behind each other, the latency of signalling the another GPU once all GPUs were kicked off would be 1/4 of a single bus solution with 4 buses.
I said awhile back that PlayStation's standout specialism is producing cheap, reliable, cutting edge solutions with higher performance interconnects, and this in a stack or lidded would need that. Moore's law is certainly making monolithic chip gains much harder, but I suspect most of the northbridge chip-chip connections like the EiB will now need to either be a stacked chip, which still sounds like a cooling issue for 4 GPUs, or that the chip-chip interconnects will have to operate in the southbridge domain, but provide a path to close the gap to give northbridge level performance.
My speculation might be all wishful thinking, and Sony might not even be looking to use that patent for the PS6, but from my thinking here, it feels tp me like it might be able to tick all the boxes they need for a meaningful performance leap without TDP issues, cooling, moore's law limitations, or cost issues being prohibitive for a £450 PS6.
